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1. general description the saa7128h; saa7129h encodes digital c r -y-c b video data to an ntsc, pal or secam cvbs or s-video signal. simultaneously, rgb or bypassed but interpolated c r -y-c b signals are available via three additional dacs. the circuit at a 54 mhz multiplexed digital d1 input port accepts two itu-r bt.656 compatible c r -y-c b data streams with 720 active pixels per line in 4:2:2m ultiplexed formats, for example mpeg decoded data with overlay and mpeg decoded data without overlay, where one data stream is latched at the rising clock edge and the other at the falling clock edge. it includes a sync/clock generator and on-chip dacs. 2. features n monolithic cmos 3.3 v device, 5 v i 2 c-bus optional n digital pal/ntsc/secam encoder n system pixel frequency 13.5 mhz n 54 mhz double-speed multiplexed d1 interface capable of splitting data into two separate channels (encoded and baseband) n three digital-to-analog converters (dacs) for cvbs (csync), vbs (cvbs) and c (cvbs) two times oversampled with 10-bit resolution (signals in brackets optional) n three dacs for red (c r ), green (y) and blue (c b ) two times oversampled with 9-bit resolution (signals in brackets optional) n an advanced composite sync is available on the cvbs output for rgb display centering n real-time control of subcarrier n cross-color reduction ?lter n closed captioning encoding and world standard teletext (wst) and north-american broadcast text system (nabts) teletext encoding including sequencer and ?lter n copy generation management system (cgms) encoding (cgms described by standard cpr-1204 of eiaj); 20 bits in lines 20/283 (ntsc) can be loaded via i 2 c-bus n fast i 2 c-bus control port (400 khz) n line 23 wide screen signalling (wss) encoding n video programming system (vps) data encoding in line 16 (50/625 lines counting) n encoder can be master or slave n programmable horizontal and vertical input synchronization phase n programmable horizontal sync output phase n internal color bar generator (cbg) saa7128h; saa7129h digital video encoder rev. 03 9 december 2004 product data sheet
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 2 of 55 philips semiconductors saa7128h; saa7129h digital video encoder n macrovision ? pay-per-view copy protection system rev. 7.01 and rev. 6.1 optional; this applies to saa7128h only. the device is protected by us patents 4631603, 4577216 and 4819098 and other intellectual property rights; use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited; please contact your nearest philips semiconductors sales of?ce for more information. n controlled rise/fall times of output syncs and blanking n on-chip crystal oscillator (3rd-harmonic or fundamental crystal) n down mode (low output voltage) or power-save mode of dacs n qfp44 package 3. quick reference data [1] at maximum supply voltage with highly active input signals. 4. ordering information table 1: quick reference data v ddd = 3.0 v to 3.6 v; t amb =0 c to 70 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current [1] - 130 150 ma i ddd digital supply current v ddd = 3.3 v [1] - 75 100 ma v i input signal voltage levels ttl compatible v o(p-p) analog output signal voltages y, c and cvbs without load (peak-to-peak value) 1.25 1.35 1.50 v r l load resistance 75 - 300 w le lf(i) low frequency integral linearity error -- 3 lsb le lf(d) low frequency differential linearity error -- 1 lsb t amb ambient temperature 0 - 70 c table 2: ordering information type number package name description version saa7128h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 saa7129h
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 3 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 5. block diagram fig 1. block diagram mhb572 i 2 c-bus interface sync/clock i 2 c-bus control 21 41 scl v dda4 42 sda 40 sa 9 to 16 mp7 to mp0 44 ttx 20 v dd(i2c) d y c a 36 v dda3 31 v dda2 28 v dda1 25 clock and timing 35 xtali i 2 c-bus control 34 xtalo 7 rcv1 8 rcv2 43 ttxrq 37 xclk 4 llc1 19 rtci cvbs (csync) 30 vbs (cvbs) 27 c (cvbs) 24 output interface encoder y fader v ssa1 22 v ssa2 32 v ssa3 33 i 2 c-bus control 3 ap 2 sp 39 v ddd3 17 v ddd2 6 v ddd1 38 v ssd3 18 v ssd2 5 v ssd1 mp a mp b mp pos mp neg mp vp switch i 2 c-bus control i 2 c-bus control i 2 c-bus control reset_n d y c b -c r c b -c r a red 23 green 26 blue 29 rgb processor i 2 c-bus control saa7128h saa7129h
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 4 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration saa7128h saa7129h res v ssa3 sp v ssa2 ap v dda3 llc1 cvbs v ssd1 blue v ddd1 v dda2 rcv1 vbs rcv2 green mp7 v dda1 mp6 c mp5 red mp4 ttx mp3 ttxrq mp2 sda mp1 scl mp0 reset_n v ddd2 v ddd3 v ssd2 v ssd3 rtci xclk v dd(i2c) v dda4 sa xtali v ssa1 xtalo 001aac194 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 table 3: pinning symbol pin type description res 1 - reserved pin; do not connect sp 2 i test pin; connected to digital ground for normal operation ap 3 i test pin; connected to digital ground for normal operation llc1 4 i line-locked clock input; this is the 27 mhz master clock v ssd1 5 supply digital ground 1 v ddd1 6 supply digital supply voltage 1 rcv1 7 i/o raster control 1 for video port; this pin receives/provides a vs/fs/fseq signal rcv2 8 i/o raster control 2 for video port; this pin provides an hs pulse of programmable length or receives an hs pulse
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 5 of 55 philips semiconductors saa7128h; saa7129h digital video encoder mp7 9 i double-speed 54 mhz mpeg port; it is an input for itu-r bt.656 style multiplexed c r -y-c b data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is then sent to the encoding part of the device; data sampled on the falling edge is sent to the rgb part of the device (or vice versa, depending on programming) mp6 10 i mp5 11 i mp4 12 i mp3 13 i mp2 14 i mp1 15 i mp0 16 i v ddd2 17 supply digital supply voltage 2 v ssd2 18 supply digital ground 2 rtci 19 i real-time control input; if the llc1 clock is provided by an saa7113 or saa7118, rtci should be connected to the rtco pin of the respective decoder to improve the signal quality v dd(i2c) 20 supply sense input for i 2 c-bus voltage; connect to i 2 c-bus supply sa 21 i select i 2 c-bus address; low selects slave address 88h, high selects slave address 8ch v ssa1 22 supply analog ground 1 for red (c r ), c (cvbs) and green (y) outputs red 23 o analog output of red (c r ) signal c 24 o analog output of chrominance (cvbs) signal v dda1 25 supply analog supply voltage 1 for red (c r ) and c (cvbs) outputs green 26 o analog output of green (y) signal vbs 27 o analog output of vbs (cvbs) signal v dda2 28 supply analog supply voltage 2 for vbs (cvbs) and green (y) outputs blue 29 o analog output of blue (c b ) signal cvbs 30 o analog output of cvbs (csync) signal v dda3 31 supply analog supply voltage 3 for blue (c b ) and cvbs (csync) outputs v ssa2 32 supply analog ground 2 for vbs (cvbs), blue (c b ) and cvbs (csync) outputs v ssa3 33 supply analog ground 3 for the dac reference ladder and the oscillator xtalo 34 o crystal oscillator output xtali 35 i crystal oscillator input; if the oscillator is not used, this pin should be connected to ground v dda4 36 supply analog supply voltage 4 for the dac reference ladder and the oscillator xclk 37 o clock output of the crystal oscillator v ssd3 38 supply digital ground 3 v ddd3 39 supply digital supply voltage 3 reset_n 40 i reset input, active low. after reset is applied, all digital i/os are in input mode; pal black burst on cvbs, vbs and c; rgb outputs set to lowest voltage. the i 2 c-bus receiver waits for the start condition. scl 41 i/(o) serial clock input (i 2 c-bus) with inactive output path sda 42 i/o serial data input/output (i 2 c-bus) ttxrq 43 o teletext request output, indicating when text bits are requested ttx 44 i teletext bit stream input table 3: pinning continued symbol pin type description
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 6 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7. functional description the digital video encoder encodes digital luminance and color difference signals into analog cvbs, s-video and simultaneously rgb or c r -y-c b signals. ntsc-m, pal-b/g, secam and sub-standards are supported. both interlaced and non-interlaced operation is possible for all standards. the basic encoder function consists of subcarrier generation and color modulation and insertion of synchronization signals. luminance and chrominance signals are ?ltered in accordance with the standard requirements of rs170a and itu-r bt.470-3 . for ease of post analog ?ltering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. the total ?lter transfer characteristics are illustrated in figure 8 to figure 13 . the dacs for y, c and cvbs are realized with full 10-bit resolution; 9-bit resolution for rgb output. the c r -y-c b to rgb dematrix can be bypassed optionally in order to provide the upsampled c r -y-c b input signals. the 8-bit multiplexed c r -y-c b formats are itu-r bt.656 (d1 format) compatible, but the sav and eav codes can be decoded optionally when the device is operated in slave mode. two independent data streams can be processed, one latched by the rising edge of llc1, the other latched by the falling edge of llc1. the purpose of that is e.g. to forward one of the data streams containing both video and on-screen display (osd) information to the rgb outputs, and the other stream containing video only to the encoded outputs cvbs and s-video. for optimum display of rgb signals through a euro-connector tv set, an early composite sync pulse (up to 31 llc1 clock periods) can be provided at the cvbs output. as a further alternative, the vbs and c outputs may provide a second and third cvbs signal. it is also possible to connect a philips digital video decoder (saa7111a, saa7113 or saa7118) to the saa7128h; saa7129h. via the rtci pin, connected to rtco of a decoder, information concerning actual subcarrier, pal-id and de?nite subcarrier phase can be inserted. the device synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. wide screen signalling data can be loaded via the i 2 c-bus and is inserted into line 23 for standards using 50 hz ?eld rate. vps data for program dependent automatic start and stop of such featured vcrs is loadable via i 2 c-bus. the ic also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with macrovision. it is also possible to load data for copy generation management system into line 20 of every ?eld (525/60 line counting). a number of possibilities are provided for setting different video parameters, such as:
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 7 of 55 philips semiconductors saa7128h; saa7129h digital video encoder ? black and blanking level control ? color subcarrier frequency ? variable burst amplitude, etc. during reset (reset_n = low) and after reset is released, all digital i/o stages are set to input mode and the encoder is set to pal mode and outputs a black burst signal on cvbs and s-video outputs, while rgb outputs are set to their lowest output voltages. a reset forces the i 2 c-bus interface to abort any running bus transfer. 7.1 versatile fader important note: whenever the fader is activated with the symp bit set to a logic 1 (enabling the detection of embedded start of active video (sav) and end of active video (eav)), codes 00h and ffh are not allowed within the actual video data (as prescribed by itu-r bt.656 ). if sav (00h) has been detected, the fader automatically passes 100% of the respective signal until sav is detected. within the digital video encoder, two data streams can be faded against each other; these data streams can be input to the double speed mpeg port, which is able to separate two independent 27 mhz data streams mp a and mp b via a cross switch controlled by edge1 and edge2. 7.1.1 con?guration examples figure 4 to figure 7 show examples on how to con?gure the fader between the input ports and the outputs, separated into the composite (and s-video) encoder and the rgb encoder. 7.1.1.1 con?guration 1 input mp a can be faded into mp b . the resulting output of the fader is then encoded simultaneously to composite (and s-video) and rgb output (rgbin = encin = 1). in this example, either mp a or mp b could be an overlay (menu) signal to be faded smoothly in and out. fig 3. cross switch mhb574 mp a mp b mp pos mp neg edge1 = 0 edge1 = 1 edge2 = 1 edge2 = 0
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 8 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.1.1.2 con?guration 2 input mp a can be faded into mp b . the resulting output of the fader is then encoded to rgb output, while the signal coming from mp b is fed directly to composite (and s-video) output (rgbin = 1, encin = 0). also in this example, either mp a or mp b could be an overlay (menu) signal to be faded smoothly in and out, whereas the overlay appears only in the rgb output connected to the tv set. 7.1.1.3 con?guration 3 input mp b is passed directly to the rgb output, assuming e.g. it contains video including overlay. mp a is equivalently passed through the inactive fader to the composite (and s-video) output, assuming e.g. it contains video excluding overlay (rgbin = 0, encin = 1). fig 4. con?guration 1 mhb575 encoder path rgb path fader output mp a mp b mp e.g. video recorder e.g. tv vp fig 5. con?guration 2 mhb576 encoder path rgb path fader output mp a mp b mp e.g. tv vp e.g. video recorder fig 6. con?guration 3 mhb577 encoder path rgb path fader bypass mp a mp b e.g. tv e.g. video recorder
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 9 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.1.1.4 con?guration 4 only mp b input is in use; its signal is both composite (and s-video) and rgb encoded (rgbin = encin = 0). 7.1.2 parameters of the fader basically, there are three independent fade factors available, allowing for the equation: output = (fadex in1) + [(1 - fadex) in2] where x = 1, 2 or 3. factor fade1 is effective, when a color in the data stream fed to the mpeg port fader input is recognized as being between key1l and key1u. that means, the color is not identi?ed by a single numeric value, but an upper and lower threshold in a 24-bit yuv color space can be de?ned. fade1 = 00h results in 100 % signal at the mpeg port fader input and 0 % signal at the fader video port input. variation of 63 steps is possible up to fade1 = 3fh, resulting in 0 % signal at the mpeg port fader input and 100 % signal at the fader video port input. factor fade2 is effective, when a color in the data stream fed to the mpeg port fader input is recognized as being between key2l and key2u. fade2 is to be seen in conjunction with a color that is de?ned by a 24-bit internal color look-up table (clut). fade2 = 00h results in 100 % of the internally de?ned lut color and 0 % signal at the fader video port input. variation of 63 steps is possible up to fade2 = 3fh, resulting in 0 % of the internally de?ned lut color and 100 % signal at the fader video port input. finally, factor fade3 is effective, when a color in the data stream fed to the mpeg port fader input is recognized as neither being between key1l and key1u nor being between key2l and key2h. fade3 = 00h results in 100 % signal at the mpeg port fader input and 0 % signal at the fader video port input. variation of 63 steps is possible up to fade3 = 3fh, resulting in 0 % signal at the mpeg port fader input and 100 % signal at the fader video port input. optionally, all upper and lower thresholds can be ignored, enabling to fade signals only against the lut color. if bit cfadm is set high, all data at the mpeg port fader are faded against the lut color, if bit cfadv is set high, all data at the video port fader are faded against the lut color. fig 7. con?guration 4 mhb578 encoder path rgb path mp a mp b e.g. video recorder e.g. tv
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 10 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.2 data manager in the data manager, a pre-de?ned color look-up table located in this block can be read out in a pre-de?ned sequence (8 steps per active video line) as an alternative to the external video data, achieving a color bar test pattern generator without the need for an external data source. 7.3 encoder 7.3.1 video path the encoder generates out of y, u and v baseband signals luminance and color subcarrier output signals, suitable for use as cvbs or separate y and c signals. luminance is modi?ed in gain and in offset (latter programmable in a certain range to enable different black level set-ups). a blanking level can be set after insertion of a ?xed synchronization pulse tip level in accordance with standard composite synchronization schemes. other manipulations used for the macrovision anti-taping process such as additional insertion of agc super-white pulses (programmable in height) are supported by the saa7128h only. in order to enable easy post analog ?ltering, luminance is interpolated from a 13.5 mhz data rate to a 27 mhz data rate, providing luminance in 10-bit resolution. the transfer characteristics of the luminance interpolation ?lter are illustrated in figure 10 and figure 11 . appropriate transients at start/end of active video and for synchronization pulses are ensured. chrominance is modi?ed in gain (programmable separately for u and v), standard dependent burst is inserted, before baseband color signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher color bandwidth, which can be made use of for y and c output. the transfer characteristics of the chrominance interpolation ?lter are illustrated in figure 8 and figure 9 . the amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. behind the succeeding quadrature modulator, color in a 10-bit resolution is provided on the subcarrier. the numeric ratio between y and c outputs is in accordance with the respective standards. 7.3.2 teletext insertion and encoding pin ttx receives a wst or nabts teletext bitstream sampled at the llc clock. two protocols are provided: ? at each rising edge of output signal (ttxrq) a single teletext bit has to be provided after a programmable delay at input pin ttx ? the signal ttxrq performs only a single low-to-high transition and remains at high-level for 360, 296 or 288 teletext bits, depending on the chosen standard. phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing suf?cient small phase jitter on the output text lines.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 11 of 55 philips semiconductors saa7128h; saa7129h digital video encoder ttxrq provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both ?elds. the internal insertion window for text is set to 360 (pal-wst), 296 (ntsc-wst) or 288 (nabts) teletext bits including clock run-in bits. the protocol and timing are illustrated in figure 23 . 7.3.3 video programming system (vps) encoding five bytes of vps information can be loaded via the i 2 c-bus and will be encoded in the appropriate format into line 16. 7.3.4 closed caption encoder using this circuit, data in accordance with the speci?cation of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per ?eld), each pair preceded by run-in clocks and framing code, are possible. the actual line number where data is to be encoded in, can be modi?ed in a certain range. the data clock frequency is in accordance with the de?nition for ntsc-m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz ?eld frequencies at 32 times horizontal line frequency. 7.3.5 anti-taping (saa7128h only) for more information contact your nearest philips semiconductors sales of?ce. 7.4 rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, c b and c r signals are de-matrixed, individual gain adjustment for y and color difference signals and 2 times oversampling for luminance and 4 times oversampling for color difference signals is performed. the transfer curves of luminance and color difference components of rgb are illustrated in figure 12 and figure 13 respectively. 7.5 secam processor secam speci?c pre-processing is achieved by a pre-emphasis of color difference signals (for gain and phase see figure 14 and figure 15 respectively). a baseband frequency modulator with a reference frequency shifted from 4.286 mhz to dc carries out secam modulation in accordance with appropriate standard or optional wide clipping limits. after hf pre-emphasis, line-by-line sequential carriers with black reference of 4.25 mhz (db) and 4.40625 mhz (dr) are generated on a dc reference carrier (anti-cloche ?lter; see figure 16 and figure 17 ) using speci?ed values for fsc programming bytes.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 12 of 55 philips semiconductors saa7128h; saa7129h digital video encoder alternating phase reset in accordance with secam standard is carried out automatically. during vertical blanking, the so-called bottle pulses are not provided. 7.6 output interface/dacs in the output interface, encoded y and c signals are converted from digital-to-analog in a 10-bit resolution. y and c signals are also combined in a 10-bit cvbs signal. the cvbs output occurs with the same processing delay (equal to 82 llc clock periods, measured from mp input to the analog outputs) as the y, c and rgb outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of conversion ranges. red, green and blue signals are also converted from digital-to-analog, each providing a 9-bit resolution. outputs of the dacs can be set together via software control to minimum output voltage (approximately 0.2 v dc) for either purpose. alternatively, the buffers can be switched into 3-state output condition; this allows for a wired and con?guration with other 3-state outputs and can also be used as a power-save mode. 7.7 synchronization the synchronization of the saa7128h; saa7129h is able to operate in two modes; slave mode and master mode. in master mode, see figure 19 , the circuit generates all necessary timings in the video signal itself, and it can provide timing signals at the rcv1 and rcv2 ports. in slave mode, it accepts timing information either from the rcv pins or from the embedded timing data of the itu-r bt.656 data stream. for the saa7128h; saa7129h, the only difference between master and slave mode is that it ignores the timing information at its inputs in master mode. thus, if in slave mode, any timing information is missing, the ic will continue running free without a visible effect. but there must not be any additional pulses (with wrong phase) because the circuit will not ignore them. in slave mode, see figure 18 , an interface circuit decides which signal is expected at the rcv1 port and which information is taken from its active slope. the polarity can be chosen. if prcv1 is logic 0, the rising slope will be active. the signal can be: ? a vertical sync (vs) pulse; the active slope sets the vertical phase ? an odd/even signal; the active slope sets the vertical phase, the internal ?eld ?ag to odd and optionally sets the horizontal phase ? a field sequence (fseq) signal; it marks the ?rst ?eld of the 4 (ntsc) or 8 (pal) or 12 (secam) ?eld sequences; in addition to the odd/even signal, it also sets the pal phase and optionally de?nes the subcarrier phase. on the rcv2 port, the ic can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 13 of 55 philips semiconductors saa7128h; saa7129h digital video encoder the horizontal phase can be set via a separate input rcv2. in the event of vs pulses at rcv1, this is mandatory. it is also possible to set the signal path to blank via this input. from the itu-r bt.656 data stream, the saa7128h; saa7129h decodes only the start of the ?rst line in the odd ?eld. all other information is ignored and may miss. if this kind of slave mode is active, the rcv pins may be switched to output mode. in slave mode, the horizontal trigger phase can be programmed to any point in the line, the vertical phase from line 0 to line 15 counted from the ?rst serration pulse in half line steps. whenever synchronization information cannot be derived directly from the inputs, the saa7128h; saa7129h will calculate it from the internal horizontal, vertical and pal phase. this gives good ?exibility with respect to external synchronization, but the circuit does not suppress illegal settings. in such an event, the odd/even information may vanish as it does in the non-interlaced modes. in master mode, the line lengths are ?xed to 1728 clocks at 50 hz and 1716 clocks at 60 hz. to allow non-interlaced frames, the ?eld lengths can be varied by 0.5 lines. in the event of non-interlace, the saa7128h; saa7129h does not provide odd/even information and the output signal does not contain the pal bruch sequence. at the rcv1 pin the ic can provide: ? a vertical sync (vs) signal with 2.5 (50 hz) or 3 (60 hz) lines duration ? an odd/even signal which is low in odd ?elds ? a field sequence (fseq) signal which is high in the ?rst ?eld of the 4 or 8 or 12 ?eld sequences. at the rcv2 pin, there is a horizontal pulse of programmable phase and duration available. this pulse can be suppressed in the programmable inactive part of a ?eld, giving a composite blank signal. the directions and polarities of the rcv ports can be chosen independently. timing references can be found in t ab le 55 and t ab le 63 . 7.8 clock the input to llc1 can either be an external clock source or the buffered on-chip clock xclk. the internal crystal oscillator can be run with either a 3rd-harmonic or a fundamental crystal frequency. 7.9 i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbit/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write and readable, except one read only status byte. the i 2 c-bus slave address is de?ned as 88h with pin 21 (sa) tied low and as 8ch with pin 21 (sa) tied high.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 14 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.10 input levels and formats the saa7128h; saa7129h expects digital y, c b and c r data with levels (digital codes) in accordance with itu-r bt.601 . for c and cvbs outputs, deviating amplitudes of the color difference signals can be compensated by an independent gain control setting, while gain for luminance is set to prede?ned values, distinguishable for 7.5 ire set-up or without set-up. the rgb, respectively c r -y-c b path features a gain setting individually for luminance (gy) and color difference signals (gcd). reference levels are measured with a color bar, 100 % white, 100 % amplitude and 100 % saturation. [1] transformation: r = y + 1.3707 (c r - 128) g=y - 0.3365 (c b - 128) - 0.6982 (c r - 128) b = y + 1.7324 (c b - 128). [2] representation of r, g and b (or c r , y and c b ) at the output is 9 bits at 27 mhz. table 4: itu-r bt.601 signal component levels color signals [1] y c b c r r [2] g [2] b [2] white 235 128 128 235 235 235 yellow 210 16 146 235 235 16 cyan 170 166 16 16 235 235 green 145 54 34 16 235 16 magenta 106 202 222 235 16 235 red 81 90 240 235 16 16 blue 41 240 110 16 16 235 black 16 128 128 16 16 16 table 5: 8-bit multiplexed format (similar to itu-r bt.601 ) time bits 0 1 2 3 4 5 6 7 sample c b 0y0 c r 0y1 c b 2y2 c r 2y3 luminance pixel number 0123 color pixel number 0 2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 15 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.11 bit allocation map table 6: slave receiver (slave address 88h) register function subaddress data byte [1] d7 d6 d5 d4 d3 d2 d1 d0 status byte (read only) 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e null 01h to 25h 0 0 0 0 0 0 0 0 wide screen signal 26h wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27h wsson 0 wss13 wss12 wss11 wss10 wss9 wss8 real-time control, burst start 28h deccol decfis bs5 bs4 bs3 bs2 bs1 bs0 burst end 29h 0 0 be5 be4 be3 be2 be1 be0 copy generation 0 2ah cg07 cg06 cg05 cg04 cg03 cg02 cg01 cg00 copy generation 1 2bh cg15 cg14 cg13 cg12 cg11 cg10 cg09 cg08 cg enable, copy generation 2 2ch cgen 0 0 0 cg19 cg18 cg17 cg16 output port control 2dh cvbsen1 cvbsen0 cvbstri ytri ctri rtri gtri btri null 2eh to 37h 0 0 0 0 0 0 0 0 gain luminance for rgb 38h 0 0 0 gy4 gy3 gy2 gy1 gy0 gain color difference for rgb 39h 0 0 0 gcd4 gcd3 gcd2 gcd1 gcd0 input port control 1 3ah cbenb 0 0 symp demoff csync mp2c vp2c key color 1 lower limit u 42h key1lu7 key1lu6 key1lu5 key1lu4 key1lu3 key1lu2 key1lu1 key1lu0 key color 1 lower limit v 43h key1lv7 key1lv6 key1lv5 key1lv4 key1lv3 key1lv2 key1lv1 key1lv0 key color 1 lower limit y 44h key1ly7 key1ly6 key1ly5 key1ly4 key1ly3 key1ly2 key1ly1 key1ly0 key color 2 lower limit u 45h key2lu7 key2lu6 key2lu5 key2lu4 key2lu3 key2lu2 key2lu1 key2lu0 key color 2 lower limit v 46h key2lv7 key2lv6 key2lv5 key2lv4 key2lv3 key2lv2 key2lv1 key2lv0 key color 2 lower limit y 47h key2ly7 key2ly6 key2ly5 key2ly4 key2ly3 key2ly2 key2ly1 key2ly0 key color 1 upper limit u 48h key1uu7 key1uu6 key1uu5 key1uu4 key1uu3 key1uu2 key1uu1 key1uu0 key color 1 upper limit v 49h key1uv7 key1uv6 key1uv5 key1uv4 key1uv3 key1uv2 key1uv1 key1uv0 key color 1 upper limit y 4ah key1uy7 key1uy6 key1uy5 key1uy4 key1uy3 key1uy2 key1uy1 key1uy0 key color 2 upper limit u 4bh key2uu7 key2uu6 key2uu5 key2uu4 key2uu3 key2uu2 key2uu1 key2uu0 key color 2 upper limit v 4ch key2uv7 key2uv6 key2uv5 key2uv4 key2uv3 key2uv2 key2uv1 key2uv0 key color 2 upper limit y 4dh key2uy7 key2uy6 key2uy5 key2uy4 key2uy3 key2uy2 key2uy1 key2uy0 fade factor key color 1 4eh 0 0 fade15 fade14 fade13 fade12 fade11 fade10 cfade, fade factor key color 2 4fh cfadem cfadev fade25 fade24 fade23 fade22 fade21 fade20
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 16 of 55 philips semiconductors saa7128h; saa7129h digital video encoder fade factor other 50h 0 0 fade35 fade34 fade33 fade32 fade31 fade30 look-up table key color 2 u 51h lutu7 lutu6 lutu5 lutu4 lutu3 lutu2 lutu1 lutu0 look-up table key color 2 v 52h lutv7 lutv6 lutv5 lutv4 lutv3 lutv2 lutv1 lutv0 look-up table key color 2 y 53h luty7 luty6 luty5 luty4 luty3 luty2 luty1 luty0 vps enable, input control 2 54h vpsen 0 encin rgbin delin vpsel edge2 edge1 vps byte 5 55h vps57 vps56 vps55 vps54 vps53 vps52 vps51 vps50 vps byte 11 56h vps117 vps116 vps115 vps114 vps113 vps112 vps111 vps110 vps byte 12 57h vps127 vps126 vps125 vps124 vps123 vps122 vps121 vps120 vps byte 13 58h vps137 vps136 vps135 vps134 vps133 vps132 vps131 vps130 vps byte 14 59h vps147 vps146 vps145 vps144 vps143 vps142 vps141 vps140 chrominance phase 5ah chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5bh gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5ch gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, real-time control, black level 5dh gainu8 decoe blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, real-time control, blanking level 5eh gainv8 decph blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5fh ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60h 0 0 0 0 0 0 0 0 standard control 61h downb downa inpi ygs secam scbw pal fise rtc enable, burst amplitude 62h rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63h fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64h fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65h fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66h fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67h l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68h l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69h l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6ah l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 rcv port control 6bh srcv11 srcv10 trcv2 orcv1 prcv1 cblf orcv2 prcv2 table 6: slave receiver (slave address 88h) continued register function subaddress data byte [1] d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 17 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] all bits labelled 0 are reserved. they must be programmed with logic 0. trigger control 6ch htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6dh htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6eh sblbn blckon phres1 phres0 ldel1 ldel0 flc1 flc0 closed caption, teletext enable 6fh ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 rcv2 output start 70h rcv2s7 rcv2s6 rcv2s5 rcv2s4 rcv2s3 rcv2s2 rcv2s1 rcv2s0 rcv2 output end 71h rcv2e7 rcv2e6 rcv2e5 rcv2e4 rcv2e3 rcv2e2 rcv2e1 rcv2e0 msbs rcv2 output 72h 0 rcv2e10 rcv2e9 rcv2e8 0 rcv2s10 rcv2s9 rcv2s8 ttx request h start 73h ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request h delay 74h ttxhd7 ttxhd6 ttxhd5 ttxhd4 ttxhd3 ttxhd2 ttxhd1 ttxhd0 csync advance, vsync shift 75h csynca4 csynca3 csynca2 csynca1 csynca0 vs_s2 vs_s1 vs_s0 ttx odd request vertical start 76h ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request vertical end 77h ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 ttx even request vertical start 78h ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 ttx even request vertical end 79h ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 first active line 7ah fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7bh lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 ttx mode, msb vertical 7ch ttx60 lal8 ttxo fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7dh 0 0 0 0 0 0 0 0 disable ttx line 7eh line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7fh line20 line19 line18 line17 line16 line15 line14 line13 table 6: slave receiver (slave address 88h) continued register function subaddress data byte [1] d7 d6 d5 d4 d3 d2 d1 d0
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 18 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.12 i 2 c-bus format [1] x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read. [2] if more than 1 byte data is transmitted, then auto-increment of the subaddress is performed. 7.13 slave receiver table 7: i 2 c-bus address; see t ab le 8 s slave address ack subaddress ack data 0 ack -------- data n ack p table 8: explanation of t ab le 7 part description s start condition slave address 1000 100x or 1000 110x [1] ack acknowledge, generated by the slave subaddress [2] subaddress byte data data byte -------- continued data bytes and acks p stop condition table 9: subaddress 26h bit symbol description 7 wss7 wide screen signalling bits: enhanced services ?eld 6 wss6 5 wss5 4 wss4 3 wss3 wide screen signalling bits: aspect ratio ?eld 2 wss2 1 wss1 0 wss0 table 10: subaddress 27h bit symbol description 7 wsson 0 = wide screen signalling output is disabled; default state after reset, 1 = wide screen signalling output is enabled. 6 - this bit is reserved and must be set to logic 0 5 wss13 wide screen signalling bits: reserved ?eld 4 wss12 3 wss11 2 wss10 wide screen signalling bits: subtitles ?eld 1 wss9 0 wss8
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 19 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 11: subaddress 28h bit symbol description 7 deccol 0 = disable color detection bit of rtci input, 1 = enable color detection bit of rtci input; bit rtce must be set to logic 1, see figure 22 6 decfis 0 = ?eld sequence as fise in subaddress 61, 1 = ?eld sequence as fise bit in rtci input; bit rtce must be set to logic 1, see figure 22 5 bs5 starting point of burst in clock cycles: pal: bs[5:0] = 33 (21h); default value after reset ntsc: bs[5:0] = 25 (19h). 4 bs4 3 bs3 2 bs2 1 bs1 0 bs0 table 12: subaddress 29h bit symbol description 7 - these 2 bits are reserved; each must be set to logic 0 6- 5 be5 ending point of burst in clock cycles: pal: be[5:0] = 29 (1dh); default value after reset ntsc: be[5:0] = 29 (1dh). 4 be4 3 be3 2 be2 1 be1 0 be0 table 13: subaddress 2ah bit symbol description 7 to 0 cg[07:00] lsb of the byte is encoded immediately after run-in, the msb of the byte has to carry the crcc bit, in accordance with the de?nition of copy generation management system encoding format table 14: subaddress 2bh bit symbol description 7 to 0 cg[15:08] second byte; the msb of the byte has to carry the crcc bit, in accordance with the de?nition of copy generation management system encoding format table 15: subaddress 2ch bit symbol description 7 cgen 0 = copy generation data output is disabled; default state after reset, 1 = copy generation data output is enabled. 6 - these 3 bits are reserved; each must be set to logic 0 5- 4-
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 20 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 3 cg19 remaining bits of copy generation code 2 cg18 1 cg17 0 cg16 table 16: subaddress 2dh bit symbol description 7 cvbsen1 0 = luminance output signal is switched to y dac; default state after reset, 1 = cvbs output signal is switched to y dac. 6 cvbsen0 0 = chrominance output signal is switched to c dac; default state after reset, 1 = cvbs output signal is switched to c dac. 5 cvbstri 0 = dac for cvbs output in 3-state mode (high-impedance), 1 = dac for cvbs output in normal operation mode; default state after reset. 4 ytri 0 = dac for y output in 3-state mode (high-impedance), 1 = dac for y output in normal operation mode; default state after reset. 3 ctri 0 = dac for c output in 3-state mode (high-impedance), 1 = dac for c output in normal operation mode; default state after reset. 2 rtri 0 = dac for red output in 3-state mode (high-impedance), 1 = dac for red output in normal operation mode; default state after reset. 1 gtri 0 = dac for green output in 3-state mode (high-impedance), 1 = dac for green output in normal operation mode; default state after reset. 0 btri 0 = dac for blue output in 3-state mode (high-impedance), 1 = dac for blue output in normal operation mode; default state after reset. table 17: subaddress 38h bit symbol description 7 to 5 - these 3 bits are reserved; each must be set to logic 0 4 to 0 gy[4:0] gain luminance of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ); suggested nominal value = - 6 (11010b), depending on external application table 18: subaddress 39h bit symbol description 7 to 5 - these 3 bits are reserved; each must be set to logic 0 4 to 0 gcd[4:0] gain color difference of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ); suggested nominal value = - 6 (11010b), depending on external application table 15: subaddress 2ch continued bit symbol description
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 21 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 19: subaddress 3ah bit symbol description 7 cbenb 0 = data from input ports is encoded; default state after reset, 1 = color bar with ?xed colors is encoded. 6 - these 2 bits are reserved; each must be set to a logic 0 5- 4 symp 0 = horizontal and vertical trigger is taken from rcv2 and rcv1, respectively; default state after reset, 1 = horizontal and vertical trigger is decoded out of itu-r bt.656 compatible data at mpeg port. 3 demoff 0 = yc b c r -to-rgb dematrix is active; default state after reset, 1=yc b c r -to-rgb dematrix is bypassed. 2 csync 0 = cvbs output signal is switched to cvbs dac; default state after reset, 1 = advanced composite sync is switched to cvbs dac. 1 mp2c 0 = input data is twos complement from mpeg port fader input, 1 = input data is straight binary from mpeg port fader input; default state after reset. 0 vp2c 0 = input data is twos complement from video port fader input, 1 = input data is straight binary from video port fader input; default state after reset. table 20: subaddresses 42h to 44h and 48h to 4ah address byte description 42h, 48h key1lu[7:0] key1uu[7:0] key color 1 lower and upper limits for u, v and y; if mpeg input signal is within the limits of key color 1 the incoming signals at the video port and mpeg port are added together according to the equation: fade1 video signal + (1 - fade1) mpeg signal default value of all bytes after reset = 80h. 43h, 49h key1lv[7:0] key1uv[7:0] 44h, 4ah key1ly[7:0] key1uy[7:0] table 21: subaddresses 45h to 47h and 4bh to 4dh address byte description 45h, 4bh key2lu[7:0] key2uu[7:0] key color 2 lower and upper limits for u, v and y; if mpeg input signal is within the limits of key color 2 the incoming signals at the video port and mpeg port are added together according to the equation: fade2 video signal + (1 - fade2) lut values default value of all bytes after reset = 80h. 46h, 4ch key2lv[7:0] key2uv[7:0] 47h, 4dh key2ly[7:0] key2uy[7:0]
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 22 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 22: subaddress 4eh bit symbol description 7 to 6 - these 2 bits are reserved; each must be set to logic 0 5 to 0 fade1[5:0] these 6 bits form factor fade1 which determines the ratio between the mpeg and video input signal in the resulting video data stream if the key color 1 is detected in the mpeg input signal: fade1 = 00h: 100 % mpeg, 0 % video fade1 = 3fh: 100 % video, 0 % mpeg; default value after reset. table 23: subaddress 4fh bit symbol description 7 cfadem 0 = fader operates in normal mode; default state after reset, 1 = the entire video input stream is faded with the color stored in the lut (subaddresses 51h to 53h) regardless of the mpeg input signal; the color keys are disabled. 6 cfadev 0 = fader operates in normal mode; default state after reset, 1 = the entire mpeg input stream is faded with the color stored in the lut (subaddresses 51h to 53h) regardless of the video input signal; the color keys are disabled. 5 to 0 fade2[5:0] these 6 bits form factor fade2 which determines the ratio between the lut color values (subaddresses 51h to 53h) and the video input signal in the resulting video data stream if the key color 2 is detected in the mpeg input signal: fade2 = 00h: 100 % lut color, 0 % video fade2 = 3fh: 100 % video, 0 % lut color; default value after reset. table 24: subaddress 50h bit symbol description 7 to 6 - these 2 bits are reserved; each must be a logic 0 5 to 0 fade3[5:0] these 6 bits form factor fade3 which determines the ratio between the mpeg and video input signal in the resulting video data stream if neither the key color 1 nor the key color 2 is detected in the mpeg input signal: fade3 = 00h: 100 % mpeg, 0 % video fade3 = 3fh: 100 % video, 0 % mpeg; default value after reset. table 25: subaddress 51h bit symbol description 7 to 0 lutu[7:0] lut for the color values inserted in case of key color 2 u detection in the mpeg input data stream; lutu[7:0] = 80h; default value after reset table 26: subaddress 52h bit symbol description 7 to 0 lutv[7:0] lut for the color values inserted in case of key color 2 v detection in the mpeg input data stream; lutv[7:0] = 80h; default value after reset
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 23 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 27: subaddress 53h bit symbol description 7 to 0 luty[7:0] lut for the color values inserted in case of key color 2 y detection in the mpeg input data stream; luty[7:0] = 80h; default value after reset table 28: subaddress 54h bit symbol description 7 vpsen 0 = video programming system data insertion is disabled; default state after reset, 1 = video programming system data insertion in line 16 is enabled. 6 - this bit is not used and should be set to logic 0 5 encin 0 = encoder path is fed with mp b input data; fader is bypassed; default state after reset, 1 = encoder path is fed with output signal of fader; see section 7.1 . 4 rgbin 0 = rgb path is fed with mp b input data; fader is bypassed; default state after reset, 1 = rgb path is fed with output signal of fader; see section 7.1 . 3 delin 0 = not supported in current version; do not use, 1 = recommended value; default state after reset. 2 vpsel 0 = not supported in current version; do not use, 1 = recommended value; default state after reset. 1 edge2 0 = mp b data is sampled on the rising clock edge; default state after reset, 1=mp b data is sampled on the falling clock edge. 0 edge1 0 = mp a data is sampled on the rising clock edge; default state after reset, 1=mp a data is sampled on the falling clock edge. table 29: subaddress 55h bit symbol description 7 to 0 vps5[7:0] ?fth byte of video programming system data in line 16; lsb ?rst table 30: subaddress 56h bit symbol description 7 to 0 vps11[7:0] eleventh byte of video programming system data in line 16; lsb ?rst table 31: subaddress 57h bit symbol description 7 to 0 vps12[7:0] twelfth byte of video programming system data in line 16; lsb ?rst table 32: subaddress 58h bit symbol description 7 to 0 vps13[7:0] thirteenth byte of video programming system data in line 16; lsb ?rst
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 24 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] all ire values are rounded up. table 33: subaddress 59h bit symbol description 7 to 0 vps14[7:0] fourteenth byte of video programming system data in line 16; lsb ?rst table 34: subaddress 5ah bit symbol description 7 to 0 chps[7:0] phase of encoded color subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees: 0fh = pal-b/g and data from input ports 3ah = pal-b/g and data from look-up table 35h = ntsc-m and data from input ports 57h = ntsc-m and data from look-up table. table 35: subaddress 5bh bit symbol description 7 to 0 gainu[7:0] these are the 8 lsbs of the 9-bit code that selects the variable gain for the c b signal; input representation in accordance with itu-r bt.601 ; see t ab le 36 ; the msb is held in subaddress 5dh; see t ab le 39 table 36: gainu values conditions [1] encoding white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal gainu[8:0] = 0 output subcarrier of u contribution = 0 gainu[8:0] = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu[8:0] = 0 output subcarrier of u contribution = 0 gainu[8:0] = 125 (7dh) output subcarrier of u contribution = nominal gainu[8:0] = 106 (6ah) nominal gainu for secam encoding table 37: subaddress 5ch bit symbol description 7 to 0 gainv[7:0] these are the 8 lsbs of the 9-bit code that selects the variable gain for the c r signal; input representation in accordance with itu-r bt.601 ; see t ab le 38 ; the msb is held in subaddress 5eh; see t ab le 41 table 38: gainv values conditions [1] encoding white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal gainv[8:0] = 0 output subcarrier of v contribution = 0 gainv[8:0] = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv[8:0] = 0 output subcarrier of v contribution = 0 gainv[8:0] = 175 (afh) output subcarrier of v contribution = nominal
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 25 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] all ire values are rounded up. [1] all ire values are rounded up. [2] output black level/ire = blckl 2/6.29 + 28.9. [3] output black level/ire = blckl 2/6.18 + 26.5. gainv[8:0] = 129 (81h) nominal gainv for secam encoding table 39: subaddress 5dh bit symbol description 7 gainu8 msb of the 9-bit code that sets the variable gain for the c b signal; see t ab le 35 . 6 decoe real-time control: 0 = disable odd/even ?eld control bit from rtci 1 = enable odd/even ?eld control bit from rtci; see figure 22 . 5 to 0 blckl[5:0] variable black level; input representation in accordance with itu-r bt.601 ; see t ab le 40 table 40: blckl values conditions [1] encoding [1] white-to-sync = 140 ire [2] recommended value: blckl = 58 (3ah) blckl = 0 [2] output black level = 29 ire blckl = 63 (3fh) [2] output black level = 49 ire white-to-sync = 143 ire [3] recommended value: blckl = 51 (33h) blckl = 0 [3] output black level = 27 ire blckl = 63 (3fh) [3] output black level = 47 ire table 41: subaddress 5eh bit symbol description 7 gainv8 msb of the 9-bit code that sets the variable gain for the c r signal; see t ab le 37 . 6 decph real-time control: 0 = disable subcarrier phase reset bit from rtci 1 = enable subcarrier phase reset bit from rtci; see figure 22 . 5 to 0 blnnl[5:0] variable blanking level; see t ab le 42 table 42: blnnl values conditions [1] encoding [1] white-to-sync = 140 ire [2] recommended value: blnnl = 46 (2eh) blnnl = 0 [2] output blanking level = 25 ire blnnl = 63 (3fh) [2] output blanking level = 45 ire white-to-sync = 143 ire [3] recommended value: blnnl = 53 (35h) blnnl = 0 [3] output blanking level = 26 ire table 38: gainv values continued conditions [1] encoding
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 26 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] all ire values are rounded up. [2] output black level/ire = blnnl 2/6.29 + 25.4. [3] output black level/ire = blnnl 2/6.18 + 25.9; default after reset: 35h. blnnl = 63 (3fh) [3] output blanking level = 46 ire table 43: subaddress 5fh bit symbol description 7 ccrs1 these 2 bits select the cross-color reduction ?lter in luminance; see t ab le 44 and figure 10 6 ccrs0 5 blnvb5 these 6 bits select the variable blanking level during vertical blanking; interval is typically identical to value of blnnl 4 blnvb4 3 blnvb3 2 blnvb2 1 blnvb1 0 blnvb0 table 44: selection of cross-color reduction ?lter ccrs1 ccrs0 description 0 0 no cross-color reduction 0 1 cross-color reduction #1 active 1 0 cross-color reduction #2 active 1 1 cross-color reduction #3 active table 45: subaddress 61h bit symbol description 7 downb 0 = dacs for r, g and b in normal operational mode, 1 = dacs for r, g and b forced to lowest output voltage; default state after reset. 6 downa 0 = dacs for cvbs, y and c in normal operational mode; default state after reset, 1 = dacs for cvbs, y and c forced to lowest output voltage. 5 inpi 0 = pal switch phase is nominal; default state after reset, 1 = pal switch phase is inverted compared to nominal if rtc is enabled; see t ab le 46 . 4 ygs 0 = luminance gain for white - black 100 ire; default state after reset, 1 = luminance gain for white - black 92.5 ire including 7.5 ire set-up of black. 3 secam 0 = no secam encoding; default state after reset, 1 = secam encoding activated; bit pal has to be set to logic 0. table 42: blnnl values continued conditions [1] encoding [1]
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 27 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] all ire values are rounded up. 2 scbw 0 = enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figure 8 and 9 ), 1 = standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figure 8 and 9 ); default state after reset. 1 pal 0 = ntsc encoding (non-alternating v component), 1 = pal encoding (alternating v component); default state after reset. 0 fise 0 = 864 total pixel clocks per line; default state after reset, 1 = 858 total pixel clocks per line. table 46: subaddress 62h bit symbol description 7 rtce 0 = no real-time control of generated subcarrier frequency; default state after reset, 1 = real-time control of generated subcarrier frequency through saa7113 or saa7118; for timing, see figure 22 . 6 to 0 bsta[6:0] amplitude of color burst; input representation in accordance with itu-r bt.601 ; see t ab le 47 table 47: bsta values conditions [1] encoding white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 63 (3fh) bsta = 0 to 2.02 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 45 (2dh) bsta = 0 to 2.82 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 67 (43h) bsta = 0 to 1.90 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 47 (2fh); default value after reset bsta = 0 to 3.02 nominal fixed burst amplitude with secam encoding table 48: subaddresses 63h to 66h address byte description 63h fsc[07:00] these 4 bytes are used to program the subcarrier frequency; fsc[31:24] is the most signi?cant byte, fsc[07:00] is the least signi?cant byte: table 45: subaddress 61h continued bit symbol description
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 28 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] examples: a) ntsc-m: f sc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal-b/g: f sc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). c) secam: f sc = 274.304, f llc = 1728 ? fsc = 681786290 (28a33bb2h). 64h fsc[15:08] f sc = subcarrier frequency (in multiples of line frequency) f llc = clock frequency (in multiples of line frequency). 65h fsc[23:16] fsc = round [1] 66h fsc[31:24] table 49: subaddress 67h bit symbol description 7 to 0 l21o[07:00] ?rst byte of captioning data, odd ?eld; lsb of the byte is encoded immediately after run-in and framing code, the msb of the byte has to carry the parity bit, in accordance with the de?nition of line 21 encoding format table 50: subaddress 68h bit symbol description 7 to 0 l21o[17:10] second byte of captioning data, odd ?eld; the msb of the byte has to carry the parity bit, in accordance with the de?nition of line 21 encoding format table 51: subaddress 69h bit symbol description 7 to 0 l21e[07:00] ?rst byte of extended data, even ?eld; lsb of the byte is encoded immediately after run-in and framing code, the msb of the byte has to carry the parity bit, in accordance with the de?nition of line 21 encoding format table 52: subaddress 6ah bit symbol description 7 to 0 l21e[17:10] second byte of extended data, even ?eld; the msb of the byte has to carry the parity bit, in accordance with the de?nition of line 21 encoding format table 53: subaddress 6bh bit symbol description 7 srcv11 these 2 bits de?ne signal type on pin rcv1; see t ab le 54 6 srcv10 5 trcv2 0 = horizontal synchronization is taken from rcv1 port (at bit symp = low) or from decoded frame sync of itu-r bt.656 input (at bit symp = high); default state after reset, 1 = horizontal synchronization is taken from rcv2 port (at bit symp = low). table 48: subaddresses 63h to 66h continued address byte description f sc f llc -------- - 2 32 ? ??
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 29 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 4 orcv1 0 = pin rcv1 is switched to input; default state after reset, 1 = pin rcv1 is switched to output. 3 prcv1 0 = polarity of rcv1 as output is active high, rising edge is taken when input; default state after reset, 1 = polarity of rcv1 as output is active low, falling edge is taken when input. 2 cblf when cblf = 0: if orcv2 = 1, pin rcv2 provides an href signal (horizontal reference pulse that is de?ned by rcv2s and rcv2e, also during vertical blanking interval); default state after reset if orcv2 = 0 and bit symp = 0, signal input to rcv2 is used for horizontal synchronization only (if trcv2 = 1); default state after reset. when cblf = 1: if orcv2 = 1, pin rcv2 provides a composite-blanking-not signal, for example a reference pulse that is de?ned by rcv2s and rcv2e, excluding vertical blanking interval, which is de?ned by fal and lal if orcv2 = 0 and bit symp = 0, signal input to rcv2 is used for horizontal synchronization (if trcv2 = 1) and as an internal blanking signal. 1 orcv2 0 = pin rcv2 is switched to input; default state after reset, 1 = pin rcv2 is switched to output. 0 prcv2 0 = polarity of rcv2 as output is active high, rising edge is taken when input, respectively; default state after reset, 1 = polarity of rcv2 as output is active low, falling edge is taken when input, respectively. table 54: selection of the signal type on pin rcv1 srcv11 srcv10 rcv1 function 0 0 vs vertical sync each ?eld; default state after reset 0 1 fs frame sync (odd/even). 1 0 fseq field sequence, vertical sync every fourth ?eld (pal = 0), eighth ?eld (pal = 1) or twelfth ?eld (secam = 1). 1 1 - not applicable table 55: subaddress 6ch bit symbol description 7 to 0 htrig[7:0] these are the 8 lsbs of the 11-bit code that sets the horizontal trigger phase related to the signal on rcv1 or rcv2 input. the 3 msbs are held in subaddress 6dh; see t ab le 56 . values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed. increasing htrig[10:0] decreases delays of all internally generated timing signals. reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig[10:0] = 4fh (79). table 53: subaddress 6bh continued bit symbol description
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 30 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 56: subaddress 6dh bit symbol description 7 htrig10 these are the 3 msbs of the horizontal trigger phase code; see t ab le 55 6 htrig9 5 htrig8 4 vtrig4 sets the vertical trigger phase related to signal on rcv1 input; increasing vtrig decreases delays of all internally generated timing signals, measured in half lines; variation range of vtrig[4:0] = 0 to 31 (1fh) 3 vtrig3 2 vtrig2 1 vtrig1 0 vtrig0 table 57: subaddress 6eh bit symbol description 7 sblbn 0 = vertical blanking is de?ned by programming of fal and lal; default state after reset, 1 = vertical blanking is forced in accordance with itu-r bt.624 (50 hz) or rs170a (60 hz). 6 blckon 0 = encoder in normal operation mode, 1 = output signal is forced to blanking level; default state after reset. 5 phres1 these 2 bits select the phase reset mode of the color subcarrier generator; see t ab le 58 4 phres0 3 ldel1 these 2 bits select the delay on luminance path with reference to chrominance path; see t ab le 59 2 ldel0 1 flc1 these 2 bits select ?eld length control; see t ab le 60 0 flc0 table 58: selection of phase reset mode phres1 phres0 description 0 0 no reset or reset via rtci from saa7113 or saa7118 if bit rtce = 1; default value after reset 0 1 reset every two lines or secam speci?c if bit secam = 1 1 0 reset every eight ?elds 1 1 reset every four ?elds table 59: selection of luminance path delay ldel1 ldel0 luminance path delay 0 0 no luminance delay; default value after reset 0 1 1 llc luminance delay 1 0 2 llc luminance delay 1 1 3 llc luminance delay
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 31 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 60: selection of ?eld length control flc1 flc0 description 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default value after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 11 table 61: subaddress 6fh bit symbol description 7 ccen1 these 2 bits enable individual line 21 encoding; see t ab le 62 6 ccen0 5 ttxen 0 = disables teletext insertion; default state after reset, 1 = enables teletext insertion. 4 sccln4 these 5 bits select the actual line where closed caption or extended data are encoded: 3 sccln3 line = (sccln[4:0] + 4) for m-systems line = (sccln[4:0] + 1) for other systems. 2 sccln2 1 sccln1 0 sccln0 table 62: selection of line 21 encoding ccen1 ccen0 line 21 encoding 0 0 line 21 encoding off; default value after reset 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds table 63: subaddress 70h bit symbol description 7 to 0 rcv2s[7:0] these are the 8 lsbs of the 11-bit code that determines the start of the output signal on the rcv2 pin; the 3 msbs of the 11-bit code are held at subaddress 72h; see t ab le 65 ; values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; leading sync slope at cvbs output coincides with leading slope of rcv2 out at rcv2s = 49h table 64: subaddress 71h bit symbol description 7 to 0 rcv2e[7:0] these are the 8 lsbs of the 11-bit code that determines the end of the output signal on the rcv2 pin; the 3 msbs of the 11-bit code are held at subaddress 72h; see t ab le 65 ; values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; leading sync slope at cvbs output coincides with trailing slope of rcv2 out at rcv2e = 49h
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 32 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 65: subaddress 72h bit symbol description 7 - this bit is reserved and must be set to a logic 0 6 rcv2e10 these are the 3 msbs of end of output signal code; see t ab le 64 5 rcv2e9 4 rcv2e8 3 - this bit is reserved and must be set to a logic 0 2 rcv2s10 these are the 3 msbs of start of output signal code; see t ab le 63 1 rcv2s9 0 rcv2s8 table 66: subaddress 73h bit symbol description 7 to 0 ttxhs[7:0] start of signal on pin ttxrq; see figure 23 : pal: ttxhs[7:0] = 42h ntsc: ttxhs[7:0] = 54h. table 67: subaddress 74h bit symbol description 7 to 0 ttxhd[7:0] indicates the delay in clock cycles between rising edge of ttxrq output and valid data at pin ttx: minimum value: ttxhd[7:0] = 2. table 68: subaddress 75h bit symbol description 7 csynca4 advanced composite sync against rgb output from 0 to 31 llc clock periods 6 csynca3 5 csynca2 4 csynca1 3 csynca0 2 vs_s2 vertical sync shift between rcv1 and rcv2 (switched to output); in master mode it is possible to shift hsync (rcv2; cblf = 0) against vsync (rcv1; srcv11 = 0 and srcv10 = 0): standard value: vs_s[2:0] = 3. 1 vs_s1 0 vs_s0 table 69: subaddress 76h bit symbol description remarks 7 to 0 ttxovs[7:0] these are the 8 lsbs of the 9-bit code that determines the ?rst line of occurrence of signal on pin ttxrq in odd ?eld. the msb is held in subaddress 7ch; see t ab le 75 : pal: ttxovs = 05h; ntsc: ttxovs = 06h line = (ttxovs[8:0] + 4) for m-systems line = (ttxovs[8:0] + 1) for other systems.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 33 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 70: subaddress 77h bit symbol description remarks 7 to 0 ttxove[7:0] these are the 8 lsbs of the 9-bit code that determines the last line of occurrence of signal on pin ttxrq in odd ?eld. the msb is held in subaddress 7ch; see t ab le 75 : pal: ttxove = 16h; ntsc: ttxove = 10h last line = (ttxove[8:0] + 3) for m-systems last line = ttxove[8:0] for other systems. table 71: subaddress 78h bit symbol description remarks 7 to 0 ttxevs[7:0] these are the 8 lsbs of the 9-bit code that determines the ?rst line of occurrence of signal on pin ttxrq in even ?eld. the msb is held in subaddress 7ch; see t ab le 75 : pal: ttxevs = 04h; ntsc: ttxevs = 05h ?rst line = (ttxevs[8:0] + 4) for m-systems ?rst line = (ttxevs[8:0] + 1) for other systems. table 72: subaddress 79h bit symbol description remarks 7 to 0 ttxeve[7:0] these are the 8 lsbs of the 9-bit code that determines the last line of occurrence of signal on pin ttxrq in even ?eld. the msb is held in subaddress 7ch; see t ab le 75 : pal: ttxeve = 16h; ntsc: ttxeve = 10h last line = (ttxeve[8:0] + 3) for m-systems last line = ttxeve[8:0] for other systems. table 73: subaddress 7ah bit symbol description 7 to 0 fal[7:0] these are the 8 lsbs of the 9-bit code that determines the ?rst active line. the msb is held in subaddress 7ch; see t ab le 75 ; fal[8:0] = 0 coincides with the ?rst ?eld synchronization pulse: ?rst active line = (fal[8:0] + 4) for m-systems ?rst active line = (fal[8:0] + 1) for other systems. table 74: subaddress 7bh bit symbol description 7 to 0 lal[7:0] these are the 8 lsbs of the 9-bit code that determines the last active line. the msb is held in subaddress 7ch; see t ab le 75 ; lal[8:0] = 0 coincides with the ?rst ?eld synchronization pulse: last active line = (lal[8:0] + 3) for m-systems last active line = lal[8:0] for other systems.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 34 of 55 philips semiconductors saa7128h; saa7129h digital video encoder table 75: subaddress 7ch bit symbol description 7 ttx60 0 = enables nabts (fise = 1) or european teletext (fise = 0); default state after reset, 1 = enables world standard teletext 60 hz (fise = 1). 6 lal8 msb of the last active line code; see t ab le 74 5 ttxo 0 = new teletext protocol selected: at each rising edge of ttxrq a single teletext bit is requested; see figure 23 ; default state after reset, 1 = old teletext protocol selected: the encoder provides a window of ttxrq going high; the length of the window depends on the chosen teletext standard; see figure 23 . 4 fal8 msb of the ?rst active line code; see t ab le 73 3 ttxeve8 msb of the 9-bit code that selects the last line of occurrence of signal on pin ttxrq in even ?eld; see t ab le 72 2 ttxove8 msb of the 9-bit code that selects the last line of occurrence of signal on pin ttxrq in odd ?eld; see t ab le 70 1 ttxevs8 msb of the 9-bit code that selects the ?rst line of occurrence of signal on pin ttxrq in even ?eld; see t ab le 71 0 ttxovs8 msb of the 9-bit code that selects the ?rst line of occurrence of signal on pin ttxrq in odd ?eld; see t ab le 69 table 76: subaddress 7eh bit symbol description 7 to 0 line[12:5] individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective line bits. disabled line = linenn (50 hz ?eld rate). this bit mask is effective only, if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve. table 77: subaddress 7fh bit symbol description 7 to 0 line[20:13] individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective line bits. disabled line = linenn (50 hz ?eld rate). this bit mask is effective only, if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 35 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 7.14 slave transmitter the slave transmitter slave address is 89h. table 78: subaddress 00h bit symbol description 7 ver2 these 3 bits form the version identi?cation number of the device: it will be changed with all versions of the ic that have different programming models; current version is 000b 6 ver1 5 ver0 4 ccrdo 1 = closed caption bytes of the odd ?eld have been encoded, 0 = the bit is reset after information has been written to the subaddresses 67h and 68h; it is set immediately after the data has been encoded. 3 ccrde 1 = closed caption bytes of the even ?eld have been encoded, 0 = the bit is reset after information has been written to the subaddresses 69h and 6ah; it is set immediately after the data has been encoded. 2 - not used; set to logic 0 1 fseq 1 = during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pal = 8 ?elds, secam = 12 ?elds), 0 = not ?rst ?eld of a sequence. 0 o_e 1 = during even ?eld, 0 = during odd ?eld. (1) scbw = 1 (2) scbw = 0 fig 8. chrominance transfer characteristic 1 f (mhz) mbe737 - 30 - 18 - 42 - 6 6 g v (db) - 54 0 14 10 12 8 246 (1) (2)
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 36 of 55 philips semiconductors saa7128h; saa7129h digital video encoder (1) scbw = 1 (2) scbw = 0 fig 9. chrominance transfer characteristic 2 (1) ccrs1 = 0; ccrs0 = 1 (2) ccrs1 = 1; ccrs0 = 0 (3) ccrs1 = 1; ccrs0 = 1 (4) ccrs1 = 0; ccrs0 = 0 fig 10. luminance transfer characteristic 1 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 1.2 f (mhz) g v (db) (1) (2) mbe735 f (mhz) mgd672 - 30 - 18 - 42 - 6 6 g v (db) - 54 0 14 10 12 8 246 (1) (2) (4) (3)
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 37 of 55 philips semiconductors saa7128h; saa7129h digital video encoder (1) ccrs1 = 0; ccrs0 = 0 fig 11. luminance transfer characteristic 2 fig 12. luminance transfer characteristic in rgb 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) f (mhz) mgb708 - 30 - 18 - 42 - 6 6 g v (db) - 54 0 14 10 12 8 246
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 38 of 55 philips semiconductors saa7128h; saa7129h digital video encoder fig 13. color difference transfer characteristic in rgb fig 14. gain of secam pre-emphasis f (mhz) mgb706 - 30 - 18 - 42 - 6 6 g v (db) - 54 0 14 10 12 8 246 f (mhz) 0 1.6 1.2 0.4 0.8 mgb705 4 6 2 8 10 g v (db) 0
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 39 of 55 philips semiconductors saa7128h; saa7129h digital video encoder fig 15. phase of secam pre-emphasis fig 16. gain of secam anti-cloche f (mhz) 0 1.6 1.2 0.4 0.8 mgb704 10 20 30 j (deg) 0 f (mhz) 0 1.6 1.2 0.4 0.8 mgb703 8 12 4 16 20 g v (db) 0
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 40 of 55 philips semiconductors saa7128h; saa7129h digital video encoder fig 17. phase of secam anti-cloche (1) htrig = 0 (2) prcv2 = 0 (3) trcv2 = 1 (4) orcv2 = 0 fig 18. sync and video input timing f (mhz) 0 1.6 1.2 0.4 0.8 mgb702 40 20 60 80 j (deg) 0 mhb579 cvbs output rcv2 input mp input 82 llc 79 llc
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 41 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 8. limiting values [1] class 2 according to eia/jesd22-114-b. [2] class a according to eia/jesd22-115-a. 9. thermal characteristics [1] the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly. an ample copper area directly under the saa7128h; saa7129h with several through-hole platings, which connect to the ground layer (four-layer board: second layer), can also reduce the effective r th(j-a) . please do not use any solder-stop varnish under the chip. in addition the usage of soldering glue with a high thermal conductance after c uring is recommended. (1) rcv2s = 0 (2) prcv2 = 0 (3) orcv2 = 1 fig 19. sync and video output timing mhb580 cvbs output rcv2 output 73 llc table 79: limiting values in accordance with the absolute maximum rating system (iec 60134). all ground pins connected together and all supply pins connected together. symbol parameter conditions min max unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v o(a) output voltage at analog output - 0.5 v dda + 0.5 v v i(d) input voltage at digital inputs or i/o pins outputs in 3-state - 0.5 +5.5 v v o(d) output voltage at digital outputs outputs active - 0.5 v ddd + 0.5 v d v ss voltage difference between v ssaall and v ssdall - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c v esd electrostatic discharge voltage human body model [1] - 2000 v machine model [2] - 150 v table 80: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air [1] 53 k/w
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 42 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 10. characteristics table 81: characteristics v ddd = 3.0 v to 3.6 v; t amb =0 c to 70 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current [1] - 130 150 ma i ddd digital supply current v ddd = 3.3 v [1] - 75 100 ma inputs: llc1, rcv1, rcv2, mp7 to mp0, rtci, sa, reset_n and ttx v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2.0 - v ddd + 0.3 v i li input leakage current - - 1 m a c i input capacitance clocks - - 10 pf data - - 8 pf i/os at high-impedance - - 8 pf outputs: rcv1, rcv2 and ttxrq v ol low-level output voltage i ol = 2 ma - - 0.4 v v oh high-level output voltage i oh = - 2 ma 2.4 - - v i 2 c-bus: sda and scl v il low-level input voltage - 0.5 - +0.3v dd(i2c) v v ih high-level input voltage 0.7v dd(i2c) -v dd(i2c) + 0.3 v i i input current v i = low or high - 10 - +10 m a v ol low-level output voltage (pin sda) i ol = 3 ma - - 0.4 v i o output current during acknowledge 3 - - ma clock timing: llc1 and xclk t llc1 cycle time [2] 34 - 41 ns d duty factor t high /t llc1 llc1 input 40 - 60 % duty factor t high /t xclk xclk output 50 % (typical) 40 - 60 % t r rise time [2] --5 ns t f fall time [2] --6 ns input timing: rcv1, rcv2, mp7 to mp0, rtci, sa and ttx t su;dat input data set-up time 6 - - ns t hd;dat input data hold time 3 - - ns crystal oscillator f n nominal frequency (usually 27 mhz) 3rd harmonic - - 30 mhz d f/f n permissible deviation of nominal frequency [3] - 50 10 - 6 - +50 10 - 6 crystal speci?cation t amb ambient temperature 0 - 70 c
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 43 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [1] at maximum supply voltage with highly active input signals. [2] the data is for both input and output direction. [3] if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/?eld frequency. [4] for full digital range, without load, v dda = 3.3 v. the typical minimum output voltage (digital zero at dac) is 0.2 v. [5] referring to peak-to-peak analog voltages resulting from identical peak-to-peak digital codes. c l load capacitance 8 - - pf r s series resistance - - 80 w c mot motional capacitance (typical) 1.5 - 20 % - 1.5 + 20 % ff c par parallel capacitance (typical) 3.5 - 20 % - 3.5 + 20 % pf data and reference signal output timing c l output load capacitance 7.5 - 40 pf t h output hold time 4 - - ns t d output delay time - - 18 ns outputs: c, vbs, cvbs and rgb v o(p-p) output signal voltage (peak-to-peak value) [4] 1.25 1.35 1.50 v d v inequality of output signal voltages [5] --2 % r int internal serial resistance 1 - 3 w r l output load resistance 75 - 300 w b output signal bandwidth of dacs - 3 db 10 - - mhz le lf(i) low frequency integral linearity error of dacs -- 3 lsb le lf(d) low frequency differential linearity error of dacs -- 1 lsb t d(pipe)(mp) total pipeline delay from mp port 27 mhz - - 82 llc table 81: characteristics continued v ddd = 3.0 v to 3.6 v; t amb =0 c to 70 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 44 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 10.1 explanation of rtci data bits refer to figure 22 : ? the hpll increment is not evaluated by the saa7128h; saa7129h. ? the saa7128h; saa7129h generates the subcarrier frequency from the fscpll increment if enabled (see last bullet). ? the pal bit indicates the line with inverted (r - y) component of color difference signal. ? if the reset bit is enabled (rtce = 1; decph = 1; phres = 00), the phase of the subcarrier is reset in each line whenever the reset bit of rtci input is set to logic 1. ? if the fise bit is enabled (rtce = 1; decfis = 1), the saa7128h; saa7129h takes this bit instead of the fise bit in subaddress 61h. fig 20. clock data timing mhb581 mp input data output data llc1 2.0 v 0.8 v t h t d t high t llc1 t su; dat t hd; dat t su; dat t hd; dat t r t f mp pos not valid 2.6 v 1.5 v 0.6 v mp neg mp pos not valid 2.4 v 0.6 v valid not valid valid the data demultiplexing phase is coupled to the internal horizontal phase. the phase of the rcv2 signal is programmed to 262 for 50 hz and to 234 for 60 hz in this example in output mode (rcv2s). fig 21. functional timing mp(n) llc c b (0) y(0) c r (0) y(1) c b (2) rcv2 mgb699
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 45 of 55 philips semiconductors saa7128h; saa7129h digital video encoder ? if the odd/even bit is enabled (rtce = 1; decoe = 1), the saa7128h; saa7129h ignores its internally generated odd/even ?ag and takes the odd/even bit from rtci input. ? if the color detection bit is enabled (rtce = 1; deccol = 1) and no color was detected (color detection bit = 0), the subcarrier frequency is generated by the saa7128h; saa7129h. in the other case (color detection bit = 1) the subcarrier frequency is evaluated out of fscpll increment. if the color detection bit is disabled (rtce = 1; deccol = 0), the subcarrier frequency is evaluated out of fscpll increment, independent of the color detection bit of rtci input. (1) saa7113 and saa7118 support rtc level 3.1. (2) sequence bit: pal: 0 = (r - y) line normal, 1 = (r - y) line inverted; ntsc: 0 = no change. (3) fise bit: 0 = 50 hz, 1 = 60 hz. (4) odd/even bit: odd_even from external. (5) color detection: 0 = no color detected, 1 = color detected. (6) reserved bits: 229 with 50 hz systems, 226 with 60 hz systems. fig 22. rtci timing 128 13 14 19 67 64 69 72 74 68 01 0 0 22 rtci hpll increment (1) fscpll increment (1) high-to-low transition count start 4 bits reserved valid sample invalid sample not used in saa7128h/29h 3 bits reserved 8/llc 001aac192 low time slot: (2) (1) (4) (5) (6) (3)
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 46 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 10.2 teletext timing time t fd is the time needed to interpolate input data ttx and insert it into the cvbs and vbs output signal, such that it appears at t ttx = 9.78 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t pd is the pipeline delay time introduced by the source that is gated by ttxrq in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high state at output pin ttxrq, a new teletext bit must be provided by the source (new protocol) or a window of ttxrq going high is provided and the number of teletext bits, depending on the chosen teletext standard, is requested at input pin ttx (old protocol). since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. time t i(ttxw) is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbit/s (pal), 296 teletext bits at a text data rate of 5.7272 mbit/s (wst) or 288 teletext bits at a text data rate of 5.7272 mbit/s (nabts). the insertion window is not opened if the control bit ttxen is logic 0. using appropriate programming, all suitable lines of the odd ?eld (ttxovs and ttxove) plus all suitable lines of the even ?eld (ttxevs and ttxeve) can be used for teletext insertion. fig 23. teletext timing t i(ttxw) t ttx t pd t fd cvbs/y ttx ttxrq (new) ttxrq (old) text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb504
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 47 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 11. application information (1) typical value. (2) for 100 100 color bar. fig 24. application circuit mhb583 2 w (1) 23 w 75 w v ssa1 to v ssa3 v dda1 to v dda3 v dda4 22, 32, 33 25, 28, 31 36 u b 0.70 v (p-p) (2) dac6 blue agnd agnd v ssd1 to v ssd3 5, 18, 38 dgnd 0.1 m f + 3.3 v analog 0.1 m f 1 nf 10 pf 10 pf 27.0 mhz 3rd harmonic x1 xtalo xtali 29 2 w (1) 23 w 75 w u g 0.70 v (p-p) (2) dac5 green agnd 26 2 w (1) 23 w 75 w u r 0.70 v (p-p) (2) dac4 red agnd 23 2 w (1) 10 w 75 w u c 0.89 v (p-p) (2) dac3 c agnd 24 2 w (1) 10 w 75 w u vbs 1.00 v (p-p) (2) dac2 vbs agnd 27 2 w (1) 4.7 w 75 w u cvbs 1.23 v (p-p) (2) dac1 cvbs agnd agnd dgnd use one capacitor for each v dda v ddd1 to v ddd3 35 34 6, 17, 39 0.1 m f 10 m h + 3.3 v digital digital inputs and outputs dgnd use one capacitor for each v ddd agnd 30 saa7128h saa7129h
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 48 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 11.1 analog output voltages the analog output voltages are dependent on the open-loop voltage of the operational ampli?ers for full-scale conversion (typical value 1.35 v), the internal series resistor (typical value 2 w ), the external series resistor and the external load impedance. the digital output signals in front of the dacs under nominal conditions occupy different conversion ranges, as indicated in t ab le 82 for a 100 100 color bar signal. values for the external series resistors result in a 75 w load. table 82: digital output signals conversion range ordering information conversion range (peak-to-peak) cvbs sync-tip to peak-carrier (digits) y (vbs) sync-tip to white (digits) rgb (y) black to white at gdy = gdc = - 6 (digits) 1016 881 712
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 49 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 12. package outline fig 25. package outline sot307-2 (qfp44) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 50 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 51 of 55 philips semiconductors saa7128h; saa7129h digital video encoder C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 83: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 52 of 55 philips semiconductors saa7128h; saa7129h digital video encoder [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 53 of 55 philips semiconductors saa7128h; saa7129h digital video encoder 14. revision history table 84: revision history document id release date data sheet status change notice doc. number supersedes saa7128h_saa7129h_3 20041209 product data sheet - 9397 750 14325 saa7128h_7129h_2 modi?cations: ? added t ab le 79 limiting v alues ? updated t ab le 80 ther mal char acter istics ? changed the type number of some referenced ics. saa7128h_7129h_2 20021015 product speci?cation - 9397 750 09727 saa7128h_7129h_1 saa7128h_7129h_1 000308 product speci?cation - 9397 750 06127
philips semiconductors saa7128h; saa7129h digital video encoder 9397 750 14325 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 9 december 2004 54 of 55 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. licenses 19. patents notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions. us 4631603 owned by macrovision corporation us 4577216 owned by macrovision corporation us 4819098 owned by macrovision corporation 20. trademarks macrovision is a registered trademark of macrovision corporation 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c-bus components purchase of philips i 2 c-bus components conveys a license under the philips i 2 c-bus patent to use the components in the i 2 c-bus system provided the system conforms to the i 2 c-bus speci?cation de?ned by koninklijke philips electronics n.v. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 9 december 2004 document number: 9397 750 14325 published in the netherlands philips semiconductors saa7128h; saa7129h digital video encoder 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 versatile fader . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.1.1 con?guration examples . . . . . . . . . . . . . . . . . . 7 7.1.1.1 con?guration 1 . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.1.1.2 con?guration 2 . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.1.3 con?guration 3 . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.1.4 con?guration 4 . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.2 parameters of the fader . . . . . . . . . . . . . . . . . . 9 7.2 data manager . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.1 video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.2 teletext insertion and encoding . . . . . . . . . . . 10 7.3.3 video programming system (vps) encoding. 11 7.3.4 closed caption encoder . . . . . . . . . . . . . . . . . 11 7.3.5 anti-taping (saa7128h only) . . . . . . . . . . . . . 11 7.4 rgb processor . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 secam processor . . . . . . . . . . . . . . . . . . . . . 11 7.6 output interface/dacs . . . . . . . . . . . . . . . . . . 12 7.7 synchronization . . . . . . . . . . . . . . . . . . . . . . . 12 7.8 clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 13 7.10 input levels and formats . . . . . . . . . . . . . . . . . 14 7.11 bit allocation map . . . . . . . . . . . . . . . . . . . . . . 15 7.12 i 2 c-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 18 7.13 slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.14 slave transmitter . . . . . . . . . . . . . . . . . . . . . . . 35 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 41 9 thermal characteristics. . . . . . . . . . . . . . . . . . 41 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 explanation of rtci data bits . . . . . . . . . . . . . 44 10.2 teletext timing . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 application information. . . . . . . . . . . . . . . . . . 47 11.1 analog output voltages . . . . . . . . . . . . . . . . . . 48 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 49 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 50 13.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 50 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 51 13.5 package related soldering information . . . . . . 51 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 53 15 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 18 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 19 patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 20 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21 contact information . . . . . . . . . . . . . . . . . . . . 54

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